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Ordering number : ENA1619
CMOS IC
LC07424LP
Overview
Audio CODEC with Video Driver
The LC07424LP is an audio CODEC that has a built-in speaker amplifier and Line amplifier and incorporates a video driver. A input line selector and ALC circuit are provided in the audio recording system. A speaker amplifier and line output are provided in the playback system. A video driver that obviates the need for an output coupling capacitor is also included to enable AV playback processing with the single chip.
Features
* Audio systems can be configured using this single chip since almost all the audio system circuits are provided. * A high-performance ALC/limiter circuit that meets a variety of different conditions is incorporated. * A wide range of different functions can be set using parameter settings.
Functions
Recording system * ADC * input to line * analog PGA * ALC Playback system * DAC * Digital filter * Speaker amplifier Video system * Video driver * LPF * Amplifier gain : stereo single circuit, Method 16bit,THD+N=-80dB(TYP, -1dBFS for input time) : stereo single circuit, MIC Amplifier output : stereo single circuit, for recording ALC, +34dB to -14dB (0.5dB step) : The ADC output is detecting phase, analog PGA is controlled automatically. : stereo single circuit, Method 16bit,THD+N=-80dB(TYP, 0dBFS for input time) : De-emphasis filter, (fs=>48kHz/44.1kHz/32kHz) : monaural single circuit, EVR block (+0dB to -65.2dB MUTE), BTL drive, 250mW (TYP 8 VDDsp=2.8V THD+N=1%) : 1 circuit. Y / C input and Video output. Compatible with changeover between the sag compensation type and DC direct-coupling type : fc=8MHz : 6.5dB1.7dB, 0.1dB/step
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
12710 SY No.A1619-1/32
LC07424LP
common * Power down * Sampling frequency * Audio data format * Microcomputer serial data format (resister setting) * Master clock : Controllable for each function block : fs=48kHz / 44.1kHz / 32kHz : I2S / forward justification / backward justification BCLK=64fs / 32fs master/slave mode : 3-wire type (chip select, clock, data) : 256fs (MCLK pin input)
Power Supply Voltage
VDDdig(digital core) VDDio(digital IO) VDDana(analog) VDDsp(speaker) VDDh(analog) VDDv(video) VDDvh(video) =1.8V(1.71 to 3.6V) =1.8V(1.71 to 3.6V) =2.8V(2.6 to 3.6V) =2.8V(2.6 to 3.6V) =4.8V(4.5 to 5.5V) =2.8V(2.6 to 3.6V) =4.8V(4.5 to 5.5V)
Package Dimensions
unit : mm(typ) 3302A
TOP VIEW 5.0 SIDE VIEW BOTTOM VIEW 0.35
5.0
0.4
40 21
0.85 MAX
SIDE VIEW
0.0 NOM
0.2
(0.7)
SANYO : VQLP40(5.0X5.0)
Pin Assignment
30
Lout_R
29
Lout_L
28
VSSh
27
Vref_H_C
26 25
VDDh SPp
24
VSSsp
23
VDDsp
22
SPn
21
N.C.
31 32 33 34 35
Lin_L Lin_R VSSana Vref_C VDDana
VSSvh VDDvh Vout Vsag
20 19 18 17 16 15 14 13 12 11
36 RESET_X 37 MCLK
LC07424LP
Vref_v_C Cin Yin VSSv VDDv G_PORT2
38 LRCLK 39 40 BCLK TESTin
DAC_Din ADC_Dout G_PORT0 G_PORT1
1
2
3
4
5
6
7
8
9
10
Top view
No.A1619-2/32
(0.7)
0.35
VDDdig
VSSdig
VDDio
CS_X
SCLK
SDin
LC07424LP
Block Diagram
Yin
6.5dB+1.7dB(0.1dB/step) BUF CLAMP PGA LPF BUF BIAS VREF(1.3V) VREF(VDDh/2) VREF(VDDana/2) SEL MIX SEL PGA 0dB to -65.2dB SP Amp AMP control to Speaker SPp SPn Video Vout Vsag
Cin
Vref_v_C Vref_H_C Vref_C
6.5dB/0dB
Lout_L Lout_R
+34dB to -14dB Lin_L PGA
ALC/Limiter ADC 16bit ALC cont. ADC 16bit DAC 16bit
VDDvh VSSvh VDDv VSSv VDDh VSSh VDDsp VSSsp
Lin_R PGA
Interface
DAC 16bit
MPU
MCLK BCLK LRCLK DAC_Din ADC_Dout CS_X SCLK SDin RESET_X TESTin Serial IF /Regster/
VDDana VSSana I2S IF VDDio VDDdig VSSdig G_PORT2 G_PORT1 G_PORT0
No.A1619-3/32
LC07424LP
Pin Description
(Note) I/O: I=> input, Is=> Schmitt input, O=> output, IOs=> Schmitt input/output
PIN No. Digital System 36 37 38 39 40 1 2 3 4 5 9 10 11 Analog system 14 15 16 17 18 22 25 27 29 30 31 32 34 Power pin, other 6 7 8 12 13 19 20 21 23 24 26 28 33 35 VDDdig VSSdig VDDio VDDv VSSv VDDvh VSSvh N.C. VDDsp VSSsp VDDh VSSh VSSana VDDana Digital power supply Digital ground Digital IO power supply Analog power supply for video driver Analog ground for video driver 4.8V system analog power supply for video driver 4.8V system analog ground for video driver No connect Speaker analog power supply Speaker analog ground 4.8V system analog power supply 4.8V system analog ground Analog ground Analog power supply I I O O O O O O O I I O Yin Cin Vref_v_C Vsag VOUT SPn SPp Vref_H_C Lout_L Lout_R Lin_L Lin_R Vref_C Y signal input C signal input Reference voltage (Video system) Connect an external capacitor Video signal output, for sag compensation. Connect an external capacitor Video signal output. Speaker output Speaker output Reference voltage (4.8V system) Connect an external capacitor Line output, Left channel Line output, Right channel Line input, Left channel Line intput, Right channel Reference voltage (2.8V system) Connect an external capacitor Is I IOs IOs I Is O Is Is Is IOs IOs O RESET_X MCLK LRCLK BCLK TESTin DAC_Din ADC_Dout CS_X SCLK SDin G_PORT0 G_PORT1 G_PORT2 Reset (negative polarity) Master Clock LR Clock (sample rate clock) Audio IF B Clock (serial data bit clock) Audio IF For IC testing (VSS fixed in normal operation) DAC serial data input Audio IF ADC serial data output Audio IF Chip select (negative polarity) Serial clock Microcontroller IF Serial data input Microcontroller IF For IC testing (open in normal operation) For IC testing (open in normal operation) For IC testing (open in normal operation) Microcontroller IF I/O Pin Name Description
Pin treatment when not using
* Keep the analog input/output pin in the OPEN state.
LIN_L, LIN_R, LOUT_L, LOUT_R, YIN, CIN, VOUT, Vsag
* Keep the digital output pin in the OPEN state. * Do not keep the digital input pin in the OPEN state.
No.A1619-4/32
LC07424LP
Pin internal equivalent circuit
Digital pin The input/output level can be set with the VDDio pin supply voltage.
VDDio VDDio P2 ADC_Dout P11 GPORT2
P37 MCLK P40 TESTin
VDDio P36 RESET_X P1 DAC_Din P3 CS_X P4 SCLK schmitt S
schmitt S
VDDio P38 LRCLK P39 BCLK P9 GPORT0 P10 GPORT1
Analog pin Speaker AMP (Note) The resistance value is the TYPvalue.
VDDsp
VREF
VDDana VDDana
P22 SPn P25 SPp
P27 Vref_H_C P34 Vref_C
VSSana VSSsp VSSana
Line IN / OUT
VDDh VDDh VDDana
500k
P31 LIN_L P32 LIN_R
20k
P29 LOUT_L P30 LOUT_R
VSSh VSSana Vref_H_C VSSh
20k
No.A1619-5/32
LC07424LP
Video
VDDvh VDDvh
VDDv VDDv
P18 VOUT
2.4k
P14 YIN
VSSvh
VSSvh
P17 Vsag
10k
VSSv VDDv VSSv
10k
VDDv
100k 1.3V
VDDv
P15 CIN P16 Vref_v_C
3.2k 35k
VSSv VSSv
VSSv
62k
VSSv
30k
No.A1619-6/32
LC07424LP
Oparating condistion
Absolute Maximum Ratings at Ta=252C, VSSvh=VSSh=VSSana=VSSsp=VSSv=VSSdig= 0V
Parameter Supply voltage (4.8V sistem) (*1) (*2) Supply voltage (2.8V sistem) (*1) (*3) Supply voltage (1.8V sistem) (*1) (*4) Analog input voltage (*5) Digital input voltage (*6) Allowable power dissipation (*7) Operating ambient temperature Storage ambient temperature VDD48 VDD28 VDD18 (*2) 4.8V system power pin: VDDh, VDDvh (*3) 2.8V system power pin: VDDana, VDDsp, VDDv (*4) 1.8V system power pin: VDDio, VDDdig, VDDio VDDdig (*5) Applicable pins: YIN, CIN, LIN_L LIN_R (*6) Applicable pins: MCLK, TESTin, RESET_X, CS_X, SCLK, SDin, BCLK, LRCLK (for the input mode), G_PORT2 / 1 / 0 (for the input mode; the output mode only in case of normal operation) (*7) Ta 80C, our standard substrate (size: 40 mm x 50 mm x 0.8 mm. In case of mounting of four-layer glass epoxy (2S2P) ) Symbol VDD48 VDD28 VDD18 VINana VINdig Pd Topr Tstg -10 -55 min -0.3 -0.3 -0.3 -0.3 -0.3 max +7.0 +4.0 +4.0 VDD28 + 0.3 VDD18 + 0.3 400 +80 +125 unit V V V V V mW C C
(*1) The supply voltage including rise/fall must maintain the following relationship:
Recommended Operating Range at VSSvh=VSSh=VSSana=VSSsp=VSSv=VSSdig=0V
Parameter Supply voltage Symbol VDDio VDDdig VDDana VDDh Inpupt high level voltage Input low level voltage Input clock frequency Input clock duty VIH VIL fMCLK DutyMCLK VDDio pin (*1) VDDdig pin (*1) VDDana, VDDv, VDDsp pin (*1) VDDh, VDDvh pin (*1) (*2) (*2) (*3) fs=32kHz (*3) fs=48kHz, 44.1kHz (*3) Analog line input dynamic range L_IN LIN_L, LIN_R pin (*4) Conditions min 1.71 1.71 2.6 4.5 (0.8)VDDio VSS 8.192 30 45 50 50 typ 1.80 1.80 2.8 4.8 max 3.6 VDDio 3.6 5.5 VDDio (0.2)VDDio 12.288 70 55 (0.9)VDDana unit V V V V V V MHz % % Vp-p
(*1) VDDh=VDDvh, VDDana=VDDsp=VDDv VDDio VDDdig (*2) Applicable pins: MCLK, TESTin, RESET_X, CS_X, SCLK, SDin, BCLK (for the input mode LRCLK (for the input mode), G_PORT2 / 1 / 0 (for the input mode; the output mode only in case of normal operation) (*3) MCLK pin 8.192MHz => 32kHz x 256 12.288MHz => 48kHz x 256 (*4) Specifications of the input selector circuit. The PGA output is not to exceed the full scale of ADC input.
Electrical Characteristics at Ta=252C, VDDh=VDDvh= 4.5 to 5.5V, VDDana=VDDsp=VDDv=2.6 to 3.6V VDDio=VDDdig=1.71 to 3.6V, VSSvh=VSSh=VSSana=VSSsp=VSSv=VSSdig=0V
Parameter Input high level current Inputp low level current Output high level voltage Output low level voltage Input leak current Symbol IIH IIL VOH1 VOL1 ILK VI=VDDio (*1) VI=VSS (*1) IOH=-1mA (*2) IOL= 1mA (*2) VI=VDDio or VSS (*3) -10 -1 (0.8)VDDio (0.2)VDDio +10 Conditions min typ max +1 unit A A V V A
(*1) Applicable pins: MCLK, TESTin, RESET_X, CS_X, SCLK, SDin, (*2) Applicable pins: ADC_DOUT BCLK, LRCLK (Output mode) G_PORT2 / 1 / 0 (For the output mode. Output mode only in case of normal operation.) (*3) Applicable pins: BCLK, LRCLK (Output mode) G_PORT2 / 1 / 0 (For the input mode. Output mode only in case of normal operation.)
No.A1619-7/32
LC07424LP
Analog Characteristics at Ta=252C, VDDh=VDDvh=4.8V, VDDana=VDDsp=VDDv=2.8V, VDDio=VDDdig=1.8V,
VSSvh=VSSh=VSSana=VSSsp=VSSv=VSSdig=0V, 0dBFS=-3.9dBV=1.8V Unless otherwise specified, fs=48kHz, signal frequency =1kHz (sin wave), measurement range=20Hz to 20kHzDAC_DIN pin input=0dBFS PGA gain setting=0dB, EVR gain setting=0dB
Analog Input / output Parameter Input voltage Input impedance Total harmonic distortion ratio and noise ADC analog Input Resolution SNR Total harmonic distortion ratio and noise Dynamic range ADC_DR ADC_RES ADC_SNR ADC_THD+N A-Weighted LIN_L pin input: -1dBFS Measured at ADC_DOUT pin LIN_L pin input: -60dBFS Measured at ADC_DOUT pin A-Weighted Inter-channel isolation Inter-channel gain mismatch PGA step width ADC_ISO ADC_LRG PGA_GSTEP LIN_L pin input, Measured at ADC_DOUT pin LIN_L pin input, Measured at ADC_DOUT pin DAC analog output Resolution SNR Total harmonic distortion ratio and noise Dynamic range DAC_DR DAC_RES DAC_SNR DAC_THD+N A-Weighted DAC_DIN pin input: 0dBFS Measured at LOUT_L pin DAC_DIN pin input: -60dBFS Measured at LOUT_L pin, A-Weighted 75 80 88 -80 -72 16 Bits dB dB 80 -0.5 0.1 0.5 100 0.5 0.9 dB dB dB 80 80 86 -80 86 -72 16 Bits dB dB dB Symbol LI_VIN LI_RIN AA_THD+N (*1) (*1) (*2) LIN_L pin input: -1dBFS Measured at LOUT_L pin 17 20 -80 Conditions min typ max 1.68 23 -72 unit V k dB
PGA variable range
PGA_GVB
-14
34
dB
88
dB
Inter-channel isolation Inter-channel gain mismatch Output voltage
DAC_ISO DAC_LRG LO_V DAC_DIN pin input: 0dBFS LINE_AMP gain setting =6.5dB Measured at LOUT_L, LOUT_R pin
80 -0.5 1.4
100 0.5 2.0 2.6
dB dB dBV
Output load resistance Output load capacity Speaker Amp EVR Gain value
LO_RL LO_CL
LOUT_L, LOUT_R pin LOUT_L, LOUT_R pin DAC_DIN pin input: -6.5dBFS Measured at SPp and SPn pins [EVR_GAIN]=3Fh [EVR_GAIN]=2Fh [EVR_GAIN]=20h [EVR_GAIN]=10h [EVR_GAIN]=00h
10 30
k pF
EVR_G
0.0 -2.2 -7.6 -22.8 -65.2
dB
Speaker Amp Total harmonic distortion ratio and noise Output level SNR Output load resistance Output load capacity SP_V SP_SNR SP_RL SP_CL DAC_DIN pin input: 0dBFS, EVR=-2.5dB (*4) DAC_DIN pin input: 0dBFS, EVR=-2.5dB (*4) SPp, SPn pin SPp, SPn pin 2.1 78 8 30 3.0 86 3.9 dBV dB pF SP_THD+N DAC_DIN pin input: 0dBFS, EVR=-2.5dB (*3)(*4) 1.0 2.0 %
(*1) Applicable pins: Line input pin LIN_L, LIN_R Analog input full-scale value of ADC (LI_VIN = 2.8V x 0.6) (*2) The TYP resistance value varies from 10k to 20k depending on the gain setting of PGA. (*3) Output 250mW (8) (*4) BTL converted value when the same signal has been set for Lch/Rch in the DAC input
No.A1619-8/32
LC07424LP
Video characteristics at Ta=252C, VDDh=VDDvh=4.8V, VDDana=VDDsp=VDDv=2.8V,
VDDio=VDDdig=1.8V, VSSvh=VSSh=VSSana=VSSsp=VSSv=VSSdig=0V Unless otherwise specified, the AC input is the sine wave.
Parameter Input range Symbol VD_YDR VD_CDR Input impedance VD_YRin VD_CRin Frequency characteristics (*1) VD_LPF VD_D1 VD_D2 VD_DG VD_DP VD_VSNR VD_CSNR VD_RL VD_C1L VD_C2L Group delay 1 (*4) Group delay 2 (*5) Gain value (*6) VD_GD1 VD_GD2 VD_G [VD_Y_GAIN]=[VD_C_GAIN]=22h [VD_Y_GAIN]=[VD_C_GAIN]=11h [VD_Y_GAIN]=[VD_C_GAIN]=00h Gain step width VD_GS [VD_Y_GAIN]=22h to 00h [VD_C_GAIN]=22h to 00h 7.2 5.5 3.8 VOUT pin AM PM Output load resistance Output load capacity Refer to Fig. 2.5.1. C1 Refer to Fig. 2.5.1. C2 Refer to Fig. 2.5.1. 20 15 8.2 6.5 4.8 0.1 140 YIN pin CIN pin YIN pin CIN pin Input signal: 8MHz (0.7Vp-p) Input signal: 20MHz (0.7Vp-p) 2nd harmonic distortion ratio 1 (*1) 2nd harmonic distortion ratio 2 (*1) Differential gain Differential phase V_S / N (*2) C_S / N (*3) Input signal: 1MHz (0.7Vp-p) Input signal: 4MHz (0.7Vp-p) -1 -1 -64 -70 -62 150 15 400 60 45 9.2 7.5 5.8 -6.0 Conditions min typ 1.0 0.7 1 100 -3.0 -40 -50 -35 0.0 -30 -40 -30 1 1 max 1.2 0.9 unit Vp-p Vp-p M k dB dB dB dB % deg. dBrms dBrms dBrms pF pF ns ns dB dB dB dB
(*1) YIN input current, as measured at VOUT pin (0dB assumed af 100kHz) (*2) Noise Spectrum measurement Measured at VOUT pin, 50% White input, frequency range (100k-5MHz) (*3) Measured at VOUT pin , 100% Red input, frequency range (10k-1MHz) (*4) Input: YIN pin, frequency range (100k-5MHz) Measurement: VOUT pin (*5) Input: CIN pin, frequency range (2MHz-5MHz) Measurement: VOUT pin (*6) Enter 100kHz (0.5Vp-p) to YIN pin and measure at VOUT pin. Enter 3.58MHz (0.5Vp-p) to CIN pin and measure at VOUT pin. Refer to Fig. 2.5.1. (Note here that C1=C2=0F)
Fig. 2.5.1 Video driver circuit 100F VOUT Vsag 1F C1 C2 75 75
Current drain at Ta=252C, VDDh=VDDvh= 4.8V, VDDana=VDDsp=VDDv=2.8V
VDDio=VDDdig=1.8V, VSSvh=VSSh=VSSana=VSSsp=VSSv=VSSdig=0V
Parameter Source current at standby 1.8V system supply current 2.8V system supply current 4.8V system supply current Symbol IddS Idd18 Idd28 Idd48 Conditions Total of the following pins; VDDio, VDDdig, VDDana, VDDsp, VDDv, VDDh, and VDDvh (*1) Total of the following pins; VDDdig and VDDio (*2) Total of the following pins; VDDana, VDDsp, and VDDv (*2) Total of the following pins; VDDh, and VDDvh (*2) (*1) RESET_X pin = 0VAfter input of clock in the MCLK pin, measure after stopping the clock. (*2) All circuits operating (Record & Playback & VIDEO) MCLK: 12.288MHz (48kHz), Audio analog input signal: no signal, video input signal: Color bar 6 mA 13 mA 5 mA min typ 10 max 100 unit A
No.A1619-9/32
LC07424LP
Digital filter characteristics at Ta=252C, VDDh=VDDvh=4.5 to 5.5V, VDDana=VDDsp=VDDv=2.6 to 3.6V
VDDio=VDDdig=1.71 to 3.6V, VSSvh=VSSh=VSSana=VSSsp=VSSv=VSSdig=0V
Parameter ADC block LPF fs=44.1kHz Passband Passband ripple Stopband Stopband attenuation ADC block HPF fs=44.1kHz Cutoff frequency DAC block LPF fs=44.1kHz Passband Passband ripple Stopband Stopband attenuation DAC block HPF fs=44.1kHz Cutoff frequency ADC_FC 0.86 Hz DAC_PB DAC_PR ADC_SB ADC_SA Input signal =24.1kHz 24.1 -58 0.015 20 kHz dB kHz dB ADC_FC 0.882 Hz ADC_PB ADC_PR ADC_SB ADC_SA Input signal =24.1kHz 24.1 -61 Gain= 0.05dB 0.05 20 kHz dB kHz dB Symbol Conditions min typ max unit
Switching Characteristics
Parameter Microcontroller serial interface timing SCLK Cycle time SCLK high period SCLK low period Data setup time Data hold time CSX rise to SCLK wait time SCLK to CSX rise wait time Rise time Fall time Audio data timing Clock phase (Note 2) Clock phase (Note 3) Deta delay time Data setup time Data hold time tPH tPH tDD tSUA tHDA 0 1T 1T 75 1 / (128fs) 75 ns ns ns ns ns tCYC tSH tSL tSU tHD tWSCLK tWCSX tSR tSF 4T 2T 2T 2T 2T 0T 4T 8T 4T 4T 4T 4T 2T 6T 50 50 ns ns ns ns ns ns ns ns ns Symbol Conditions min typ max unit
Note 1: T = 1 / fMCLK, fMCLK: Frequency of MCLKIN pin; example: when fMCLK = 10MHz, T = 100ns, 2T = 200ns Note 2: LRCK and BCLK are inputs in Slave mode. The MCLK timing needs only to be synchronized only with LRCK and BCLK and its phase is irrelevant. Note 3: In master mode, LRCK and BCLK are output in master mode and fs is the sampling frequency. Note 4: The load of output pin: 30pF.
No.A1619-10/32
LC07424LP
Microcontroller Serial Interface Timing Diagram CS_X
tCYC tWSCLK tWCSX
tSH
tSL
SCLK
tSU tHD tSF tSR tSU tHD Dn [0]
SDin
A [7]
Audio Data Timing Diagram LRCLK
tPH tPH
BCLK
tDD
ADC_DOUT
tSUA tHDA
DAC_DIN
Input / Output level
VDDh=VDDvh=4.8V, VDDana=VDDsp=VDDv=2.8V, VDDio=VDDdig=1.8V, standard setting DAC analog output full scale (FS) FS = -4.5dBV = 1.68Vp-p = 2.8V 0.6 ADC analog input full scale (FS) FS = -4.5dBV = 1.68Vp-p = 2.8V 0.6
dB
: Gain value
0dBV=1Vrms=2.83Vp-p
Speaker output PGA
DAC DAC
SEL L_c R_c
-2dB -2dB
MIX
EVR
SP Amp (BTL) SPp SPn
6dB<*1> 4dB
0dB to -65.2dB
-2.5dBFS -7dBV
-
0dB -3dBV *1 Added in the case of commonmode signal to become the double (6dB) level. LINE Amp
BTL AMP of -3dBV input Output equivalent to 3dBV (250mW)
Line output
DAC DAC
L_c R_c
LOUT_L LOUT_R
6.5dB / 0dB
0dBFS -4.5dBV
-4.5dBV
6.5d
2dBV (=3.56Vp-p)
2dBV
No.A1619-11/32
LC07424LP
Digital output LIN_L
ALC (PGA)
+34dB to -14dB
ADC
ADC_DOUT
-1dBFS -5.5dBV
0dB
-5.5dBV
-1dBFS
Outline of operation
1. System reset/power-down When the RESET_X pin is set to "VSS," the system is reset, and all the circuits go into the power-down mode. After the power is turned on, perform this operation once without fail. When the system is reset, the contents of the register are initialized. (See register tables.) For the subsequent startup of each function, refer to the section "Control/start/stop sequence for reducing pop noise." 2. ALC When the ALC is active, the PGA (programmable gain amplifier) gain value is automatically adjusted so that the audio level becomes the preset value. The PGA gain can be adjusted in a range from +34 to -14dB. By limiting the gain adjustment range to 0 to -14dB, this adjustment function can be made to work as a limiter function. The ALC operation can be stopped by a register setting. The ALC is then placed in the manual mode, and the PGA gain is adjusted by the register setting. For details, refer to the section "Description of ALC/limiter operation." 3. A/D converter The A/D converter converts the analog PGA output signals into digital data, and the digital data is then output as 16bit serial audio data. There are three formats supported: I2S, left justification and right justification. The A/D converter incorporates a high-pass filter for canceling DC offset. The analog input range of the ADC is 0.6VDDadc. When VDDadc is 2.8V, 0dBfs is 1.68V. 4. D/A converter The D/A converter converts the digital 16-bit serial audio data into analog signals. There are three formats supported: I2S, left justification and right justification. The D/A converter incorporates a high-pass filter for canceling DC offset. The analog input range of the ADC is 0.6VDDadc. When VDDadc is 2.8V, 0dBfs is 1.68V. 5. Selector This selector is for selecting either the DAC or PGA output of the ALC. When the DAC output has been selected, the DAC output signals are output as the Line/speaker amplifier output signals. When the PGA output has been selected, the signals from line input are all turned into analog signals to become the Line/speaker amplifier output signals. 6. MIX This is the mixing circuit for the left- and right-channel audio signals. In other words, this functions as a monaural signal generator circuit to provide a monaural speaker amplifier input. The left- and right-channel signals are mixed on a 1:1 basis and then output through the -2dB amplifier. If the left- and right-channel signals are identical, the total gain becomes 4dB (= 6dB(doubled) -2dB).
No.A1619-12/32
LC07424LP
7. SP AMP This is the monaural speaker amplifier. Its maximum output is 250mW (typ VDD =2.8V, 8, THD+N = 10%). This amplifies the MIX circuit output. EVR (+0dB to -65.2dB) is mounted. A thermal shutdown function is provided. When it is left enabled, the speaker amplifier operation is automatically shut down when the chip temperature has reached a high level. 8. Video driver Either the sag compensation type or DC direct coupling type is selectable. The gain adjustment circuit (6.5dB1.7dB, 0.1dB/step) is mounted. 9. Register settings This is a 3-line system serial control circuit. The three lines are CS_X (Chip Select/low active), SCLK (Serial Clock) and SDin (Serial Data). Data can only be written into the register: The register data cannot be read out. The data transfer rate--in other words, the maximum SCLK frequency--depends on the MCLK pin clock. For details, refer to the section "Switching characteristics." 10. Master clock The master clock frequency is 256fs. This clock signal must be input from the MCLK pin. 11. Audio data formats I2S, left justification and right justification modes are supported. It is possible to select master or slave mode for BCLK and LRCLK. For details, refer to the section "Audio data formats." Microcontroller Serial Interface The internal registers values are written by the serial interface consisting of the three CS_X, SCLK, and SDin lines. When the CS_X pin is set low, the LC07424LP is switched into the mode that enables operation. The data is received on a byte basis with MSB first. Continuous access (burst access) is also possible, and the addresses incremented by 1 are accessed in sequence with each byte following access to the register specified by the address byte. If the size of data exceeding the highest address (1Dh) is accessed in this process, the data concerned is treated as invalid. In other word, the address never wraps around to 00 (HEX). The maximum data transfer rate (maximum SCLK frequency) depends on the MCLK pin clock. Refer to the section "Switching characteristics." Transferring data to one address Data (D) is written in address (A)
CS_X SCLK SDin
X X
A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
A [7:0] D [7:0] X
: Designated address : Register data : Invalid
X X
X
X
ADDRESS BYTE
WRITE DATA (address A)
Transferring data to contiguous addresses Data (D0) is written in address (A), and data (D1) is written into address (A+1).
CS_X SCLK SDin
X X
A[7] A A[6] A A[5] A A[4] A A[3] g A[2] A A[1] A A[0] D0[7] D0[6] D0[5] D0[4] D0[3] D0[2] D0[1] D0[0] D1[7] D1[6] D1[5] D1[4] D1[3] D1[2] D1[1] D1[0] A D D D D D D D D D D D D D D D D Dn[0] D
X X
ADDRESS BYTE
WRITE DATA (address A)
WRITE DATA (address A+1)
No.A1619-13/32
LC07424LP
Audio Data Formats
The timing chart is shown below. For all settings, data is MSB-first, 2'S-compliment. Slave Mode [ADF_MASTER]=0 MCLK pin LRCLK pin BCLK pin BCLK=64fs I2S mode LRCLK BCLK ADC_DOUT X DAC_DIN
15 14 Lch Data 1 0 15 14 Rch Data 1 0 [ADF_MODE] 11 10 01 00 10 01 00 [ADF_32FS] 1 1 1 0 0 0 Set prohibition Backward justification 32fs Forward justification 32fs I S 32fs Backward justification 64fs Forward justification 64fs I S 64fs
2 2
Master Mode [ADF_MASTER]=1 Input Output Output
Input Input Input
Forward justification mode LRCLK BCLK ADC_DOUT DAC_DIN
15 14 Lch Data 1 0 15 14 Rch Data 1 0 15
Backward justification mode LRCLK BCLK ADC_DOUT X DAC_DIN BCLK=32fs I2S mode LRCLK BCLK ADC_DOUT X DAC_DIN
1 0 15 14 13 Lch Data 3 2 1 0 15 14 13 Rch Data 3 2 1 0 0 15 14 Lch Data 1 0 15 14 Rch Data 1 0
Forward/backward justification mode LRCLK BCLK ADC_DOUT X DAC_DIN
0 15 14 13 Lch Data 3 2 1 0 15 14 13 Rch Data 3 2 1 0 15
No.A1619-14/32
LC07424LP
Register Table
ADRS (Address): displayed in hexadecimal notation Init (initial value): displayed in hexadecimal notation "0" settings are used for registers indicated with "0". Registers with gray background are for LSI test. They are fixed at INIT values. Set data for all registers (including registers for test).
Function PM1 PM2 ALC1 ALC2 ALC3 ALC4 ALC5 ALC6 TEST0 CODEC1 CODEC2 SEL/MIX SP1 TEST1 SP3 LINE TEST2 TEST3 VIDEO1 VIDEO2 VIDEO3 TEST4 TEST5 TEST6 TEST7 TEST8 TEST9 TEST10 TEST11 TEST12 ADRS [7:0] 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh INIT [7:0] 00h 00h 11h 3Dh 86h 1Ch 1Ch 1Ch 00h 00h 00h A3h 00h 00h 2Fh 0Fh 00h 00h 11h 11h 02h 11h 02h 00h 05h 00h FFh 00h 00h 00h 7 VREF_BIAS[1] SP_OUTEN 0 ALC_VAL[2] ALC_ZCD ALC_OFF ALC_MUTE_L ALC_MUTE_R TEST0[7] 0 ADF_DAC_INV SEL_L[1] 0 TEST1[7] 0 0 TEST2[7] TEST3[7] 0 0 0 TEST4[7] TEST5[7] TEST6[7] TEST7[7] TEST8[7] TEST9[7] TEST10[7] TEST11[7] TEST12[7] 6 VREF_BIAS[0] SP_PDX 0 ALC_VAL[1] ALC_ZCDTM[1] ALC_VMAX[6] ALC_DVL[6] ALC_DVR[6] TEST0[6] 0 ADF_ADC_INV SEL_L[0] 0 TEST1[6] 0 0 TEST2[6] TEST3[6] 0 0 0 TEST4[6] TEST5[6] TEST6[6] TEST7[6] TEST8[6] TEST9[6] TEST10[6] TEST11[6] TEST12[6] 5 SYNC_CLR MIX_PDX 0 ALC_VAL[0] ALC_ZCDTM[0] ALC_VMAX[5] ALC_DVL[5] ALC_DVR[5] TEST0[5] 0 0 SEL_R[1] SP_GAIN_L[5] TEST1[5] SP_ZCD 0 TEST2[5] TEST3[5] VD_Y_GAIN[5] VD_C_GAIN[5] 0 TEST4[5] TEST5[5] TEST6[5] TEST7[5] TEST8[5] TEST9[5] TEST10[5] TEST11[5] TEST12[5] Register Data D[7:0] 4 SEL_PDX 0 ALC_LI_L ALC_FA[1] ALC_FULLEN ALC_VMAX[4] ALC_DVL[4] ALC_DVR[4] TEST0[4] ADF_BCLK DE_EN SEL_R[0] SP_GAIN_L[4] TEST1[4] SP_ZCDTM[1] 0 TEST2[4] TEST3[4] VD_Y_GAIN[4] VD_C_GAIN[4] 0 TEST4[4] TEST5[4] TEST6[4] TEST7[4] TEST8[4] TEST9[4] TEST10[4] TEST11[4] TEST12[4] 3 ALC_PDX LO_PDX 0 ALC_FA[0] ALC_ATLIM[1] ALC_VMAX[3] ALC_DVL[3] ALC_DVR[3] TEST0[3] 0 ADF_FS[1] 0 SP_GAIN_L[3] TEST1[3] SP_ZCDTM[0] LO_DET_VDD TEST2[3] TEST3[3] VD_Y_GAIN[3] VD_C_GAIN[3] 0 TEST4[3] TEST5[3] TEST6[3] TEST7[3] TEST8[3] TEST9[3] TEST10[3] TEST11[3] TEST12[3] 2 ADC_A_PDX ADC_D_PDX 0 ALC_FR[2] ALC_ATLIM[0] ALC_VMAX[2] ALC_DVL[2] ALC_DVR[2] TEST0[2] 0 ADF_FS[0] 0 SP_GAIN_L[2] TEST1[2] SP_SOFTSW LO_GAIN TEST2[2] TEST3[2] VD_Y_GAIN[2] VD_C_GAIN[2] 0 TEST4[2] TEST5[2] TEST6[2] TEST7[2] TEST8[2] TEST9[2] TEST10[2] TEST11[2] TEST12[2] 1 DAC_A_PDX DAC_D_PDX 0 ALC_FR[1] ALC_RWT[1] ALC_VMAX[1] ALC_DVL[1] ALC_DVR[1] TEST0[1] ADF_MODE[1] ADF_LB MIX_MONO[1] SP_GAIN_L[1] TEST1[1] SP_SSC[1] LO_VREFSW TEST2[1] TEST3[1] VD_Y_GAIN[1] VD_C_GAIN[1] VD_SAG_MODE TEST4[1] TEST5[1] TEST6[1] TEST7[1] TEST8[1] TEST9[1] TEST10[1] TEST11[1] TEST12[1] 0 VIDEO_PDX SP_EVR_PDX ALC_LI_R ALC_FR[0] ALC_RWT[0] ALC_VMAX[0] ALC_DVL[0] ALC_DVR[0] TEST0[0] ADF_MODE[0] ADF_MASTER MIX_MONO[0] SP_GAIN_L[0] TEST1[0] SP_SSC[0] LO_MUTE TEST2[0] TEST3[0] VD_Y_GAIN[0] VD_C_GAIN[0] 0 TEST4[0] TEST5[0] TEST6[0] TEST7[0] TEST8[0] TEST9[0] TEST10[0] TEST11[0] TEST12[0]
ADRS INIT PM ALC ADC DAC EVR ADF
=Address =Initial value =Power Management =Automatic Level Control =AD Converter =DA Converter =Electronic Variable Resistor =Audio Data Format
PGA Lch Rch 2^n Nh Nb ABC[n]
=Programmable Gain Amplifier =Left channel =Right channel =2n (ex. 2^10 = 1024) = N denotes a hexadecimal number. = N denotes a binary number. = Register with a multiple number of bits. ABC is the register name, and "n" is the number of bits.
No.A1619-15/32
LC07424LP
Register Description (Note) This section deals with the outline. Be sure to confirm the description here by referring to the page dealing with the detailed explanation.
ADRS 00h Bit [7] [6] [5] [4] [3] [2] [1] [0] 01h [7] [6] [5] [4] [3] [2] [1] [0] 02h [7] [6] [5] [4] [3] [2] [1] [0] 03h [7] [6] [5] [4] [3] [2] [1] [0] 04h [7] [6] [5] [4] [3] [2] [1] [0] 05h [7] [6] [5] [4] [3] [2] [1] [0] ALC_OFF ALC_VMAX 0b 1Ch ALC_RWT 10b ALC_FULLEN ALC_ATLIM 0b 01b ALC_ZCD ALC_ZCDTM 1b 00b ALC_FR 101b ALC_FA 11b SYNC_CLR SEL_PDX ALC_PDX ADC_A_PDX DAC_A_PDX VIDEO_PDX SP_OUTEN SP_PDX MIX_PDX 0 LO_PDX ADC_D_PDX DAC_D_PDX SP_EVR_PDX 0 0 0 ADC_LIN_L 0 0 0 ADC_LIN_R ALC_VAL 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 1b 0b 0b 0b 1b 001b Name VREF_BIAS INIT 00b Description Setting the common reference voltage circuit 11: Normal operation 10: Rapid charging 01: pull-down 00: Power down Digital block synchronous reset control Selector block power DOWN ALC block power down ADC Analog block power down DAC Analog block power down VIDEO power down Speaker out enable Speaker power down MIX Power down 0: Fixed Line out power down ADC logic block power down DAC logic block power down 0: Fixed 0: Fixed 0: Fixed Lch line Input selection 0: Non-selection 1: Selection 0: Fixed 0: Fixed 0: Fixed Rch line Input selection 0: Non-selection 1: Selection ALC circuit, ALC value (limiter level) setting 111:-10dBFS 110: -9dBFS 101: -8dBFS 100: -7dBFS 011: -6dBFS 010: -5dBFS 001: -4dBFS 000: -3dBFS ALC circuit, Attack factor setting 11: (1 / 8)dB 10: (1 / 4)dB 01: (1 / 2)dB 00: (1 / 1)dB ALC circuit, Recovery factor setting 111: (1 / 2^14)dB 110: (1 / 2^13)dB 101: (1 / 2^12)dB 100: (1 / 2^11)dB 011: (1 / 2^10)dB 010: (1 / 2^9)dB 001: (1 / 2^8)dB 000: (1 / 2^7)dB ALC circuit, Gain change in the zero cross timing 1: ON 0: OFF 1: Normal operation 1: Normal operation 1: Normal operation 0: Power down 0: Power down 0: Power down 1: Reset 0: Norma l: operation 0: Power down 0: Power down 0: Power down 0: Power down 0: Power down 1: Normal operation 0: Power down 0: Power down 1: Normal operation 1: Normal operation 1: Normal operation 1: Normal operation 1: Normal operation 0: Speaker output stop 1: Normal operation 1: Normal operation
Speaker EVR power down 1: Normal operation 0: Fixed at [SP_GAIN]=00h
ALC circuit, Timeout time setting at detection of zero cross 11: 8192 (1 / fs) 10: 4096 (1 / fs) 01: 2048 (1 / fs) 00: 1024 (1 / fs) ALC circuit, Full-scale detection operation setting 11: 16 10: 8 01: 4 00: 2 ALC circuit, standby time setting during recovery operation 11: 2048 (1 / fs) 10: 1024 (1 / fs) 01: 512 (1 / fs) 00: 256 (1 / fs) ALC circuit 1: ALC function OFF (Manual mode) 0: ALC function ON ALC circuit, Maximum gain value setting of PGA when the ALC function is ON 7Fh to 61h: Set prohibition 60h: +34dB to 0.5dB step 1Ch: 0dB to 0.5dB step 00h: -14dB 1: ON 0: OFF ALC circuit, Limit setting for attach operation frequency between zero crosses
No.A1619-16/32
LC07424LP
ADRS 06h Bit [7] [6] [5] [4] [3] [2] [1] [0] 07h [7] [6] [5] [4] [3] [2] [1] [0] 08h 09h [7:0] [7] [6] [5] [4] [3] [2] [1] [0] 0Ah [7] [6] [5] [4] [3] [2] [1] [0] 0Bh [7] [6] [5] [4] [3] [2] [1] [0] 0Ch [7] [6] [5] [4] [3] [2] [1] [0] 0 0 SP_GAIN 0b 0b 00h 0 0 MIX_MONO 0b 0b 11b SEL_R 10b ADF_LB ADF_MASTER SEL_L ADF_DAC_INV ADF_ADC_INV 0 DE_EN ADF_FS 0b 0b 0b 0b 0b 0b 0b 0b 10b ADF_MODE 00b ADF digital audio data format setting 11, 10: Backward justification 01: Forward justification 00: I2S DAC input data inverse setting 0: Fixed De-Emphasis Filter Enable setting Sampling frequency setting 11: Set prohibition 10: 44.1kHz 01: 32kHz Loopback mode setting BCLK / LRCLK 1: ON 00: 48kHz 0: OFF 1: ON 0: OFF 1: Inverted 0: Non-inversion ADC output data inverse setting 1: Inverted 0: Non-inversion TEST0 0 0 0 ADF_BCLK 0 00h 0b 0b 0b 0b 00b ALC_MUTE_R ALC_DVR 0b 1Ch Name ALC_MUTE_L ALC_DVL INIT 0b 1Ch ALC circuit, Lch mute setting Description 1: ON 0: OFF ALC circuit, Lch PGA gain value setting in the manual mode 7Fh: MUTE 7Eh to 61h: Set prohibition 60h: +34dB to 0.5dB step 1Ch: 0dB to 0.5dB step 00h: -14dB ALC circuit, Rch mute setting 1: ON 0: OFF
ALC circuit, Rch PGA gain value setting in the manual mode 7Fh: MUTE 7Eh to 61h: Set prohibition 60h: +34dB to 0.5dB step 1Ch: 0dB to 0.5dB step 00h: -14dB For LSI TEST 0: Fixed 0: Fixed 0: Fixed ADF bit clock frequency setting 0: Fixed 1: 32fs 0: 64fs
1: Master mode 0: Slave mode
Select circuit (Lch) ALC / PGA, DAC select setting 10: DAC output selection 01: ALC / PGA output selection 11, 00: Set prohibition Select circuit (Rch) ALC / PGA, DAC select setting 10: DAC output selection 01: ALC / PGA output selection 11, 00: Set prohibition 0: Fixed 0: Fixed MIX circuit setting 11: Lch+Rch selected 10: Rch selected 01: Lch selected 00: Set prohibition 0: Fixed 0: Fixed Speaker circuit EVR gain setting 3Fh: 0dB (about 0.1 to 3.0dB / step) to 00h: -65.2dB
No.A1619-17/32
LC07424LP
ADRS 0Dh 0Eh Bit [7:0] [7] [6] [5] [4] [3] [2] [1] [0] 0Fh [7] [6] [5] [4] [3] [2] [1] [0] 10h 11h 12h [7:0] [7:0] [7] [6] [5] [4] [3] [2] [1] [0] 13h [7] [6] [5] [4] [3] [2] [1] [0] 14h [7] [6] [5] [4] [3] [2] [1] [0] 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] 0 0 0 0 0 0 VD_SAG_MODE 0 TEST4 TEST5 TEST6 TEST7 TEST8 TEST9 TEST10 TEST11 TEST12 0b 0b 0b 0b 0b 0b 1b 0b 11h 02h 00h 05h 00h FFh 00h 00h 00h 0 0 VD_C_GAIN 0b 0b 11h 0 0 0 0 LO_DET_VDD LO_GAIN LO_VREFSW LO_MUTE TEST2 TEST3 0 0 VD_Y_GAIN 0b 0b 0b 0b 1b 1b 1b 1b 00h 00h 0b 0b 11h SP_SOFTSW SP_SSC 1b 11b 0 0 SP_ZCD SP_ZCDTM Name TEST1 INIT 00h 0b 0b 1b 01b For LSI TEST 0: Fixed 0: Fixed Speaker amplifier circuit, Zero cross detection setting 1: ON 0: OFF Speaker amplifier circuit, Time setting at the zero cross time 11: 1024 (1 / fs) 10: 512 (1 / fs) 01: 256 (1 / fs) 00: 128 (1 / fs) Speaker amplifier circuit, Soft switch function setting 11: 200ms 10: 100ms 01: 50ms 00: 10ms 0: Fixed 0: Fixed 0: Fixed 0: Fixed Line output, VDDh power detection function 1: ON Line output, Gain setting Line output, MUTE setting For LSI TEST For LSI TEST 0: Fixed 0: Fixed YIN pin signal gain setting, 3Fh to 23h: Set prohibition 22h: 8.2dB to to 0: Fixed 0: Fixed CIN pin signal gain setting 3Fh to 23h: Set prohibition 22h: 8.2dB to to 0: Fixed 0: Fixed 0: Fixed 0: Fixed 0: Fixed 0: Fixed Video driver, Operation setting 1: Sag compensation 0: DC direct coupling 0: Fixed For LSI TEST For LSI TEST For LSI TEST For LSI TEST For LSI TEST For LSI TEST For LSI TEST For LSI TEST For LSI TEST (about 0.1dB / step) (about 0.1dB / step) 11h: 6.5dB 00h: 4.8dB (about 0.1dB / step) (about 0.1dB / step) 11h: 6.5dB 00h: 4.8dB 1: 6.5dB 0: 0dB 1: ON 0: OFF 0: OFF 1: ON 0: OFF Speaker amplifier circuit, Time setting of soft switch operation Description
Line output, pin state control 1: Connected with VREF 0: Not connected with VREF
No.A1619-18/32
LC07424LP
Detailed Description of Registers
Reference voltage generator circuit VREF_BIAS: Voltage REFerence BIAS
ADRS 00h Bit [7: 6] Name VREF_BIAS[1: 0] INIT 00b 11: Normal operation *1 10: VREF Rapid charging*1 01: VREF pull-down 00: Power down "9.1 Reference power supply, Line-out start / stop sequence" on page 31. *1"VREF rapid charge"setting allows rapid arrival at the target voltage through connection of resistor. "Normal operation" setting enables power-saving operation through connection of standard resistor. Description Common reference voltage circuit setting (Vref_H_C and Vref_C pins)
Logic synchronization clear
SYNC_CLR: SYNChronus CLeaR
ADRS 00h Bit [5] Name SYNC_CLR INIT 0b 1: Reset 0: Normal operation This is used if the logic operation should become unstable, and not used normally. Description Digital block synchronized reset control
Power down circuit, Speaker output Control
SEL_PDX ALC_PDX ADC_A_PDX DAC_A_PDX VIDEO_PDX SP_OUTEN SP_PDX MIX_PDX LO_PDX ADC_D_PDX DAC_D_PDX SP_EVR_PDX
ADRS 00h Bit [4] [3] [2] [1] [0] 01h [7] [6] [5] [4] [3] [2] [1] [0]
: SELector Power Down (low active) : ALC Power Down (low active) : ADC Analog Power Down (low active) : DAC Analog Power Down (low active) : VIDEO Power Down (low active) : SPeaker OUTput ENable : SPeaker amp Power Down (low active) : MIXer Power Down (low active) : Line Out Power Down (low active) : ADC Digital Power Down (low active) : DAC Digital Power Down (low active) : SPeaker EVR Power Down (low active)
Name SEL_PDX ALC_PDX ADC_A_PDX DAC_A_PDX VIDEO_PDX SP_OUTEN SP_PDX MIX_PDX 0 LO_PDX ADC_D_PDX DAC_D_PDX SP_EVR_PDX INIT 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b Selector block power down ALC block power down ADC analog block power down DAC analog block power down VIDEO power down Speaker out enable Speaker power down MIX power down 0: Fixed Line out power down ADC digital block power down DAC digital block power down 1: Normal operation 0: Power down 1: Normal operation 0: Power down 1: Normal operation 0: Power down Description 1: Normal operation 0: Power down 1: Normal operation 0: Power down 1: Normal operation 0: Power down 1: Normal operation 0: Power down 1: Normal operation 0: Power down 0: Speaker output stop 1: Normal operation 1: Normal operation 0: Power down 1: Normal operation 0: Power down
Speaker EVR power down 1: Normal operation 0: Fixed at [SP_GAIN]=00h
When the circuit concerned is not used and the power saving function is to be made effective for this circuit, turn ON the power DOWN function.
No.A1619-19/32
LC07424LP
Corresponding position diagram between Power Down registers and function blocks (for reference)
Yin
6.5dB+1.7dB(0.1dB/step) BUF CLAMP PGA LPF BUF BIAS VREF(1.3V) VREF(VDDh/2) VREF(VDDana/2) PGA Video Vout Vsag
Cin
Vref_v_C Vref_H_C Vref_C
[VIDEO_PDX]
0dB to -65.2dB
[SP_PDX]
to Speaker SPp SPn
[SEL_PDX]
SEL MIX SEL
SP Amp AMP control 6.5dB/0dB
[VREF_BIAS]
[MIX_PDX] [LO_PDX] [ALC_PDX]
+34dB to -14dB Lin_L PGA ALC/Limiter ADC 16bit ALC cont. ADC 16bit
Lout_L Lout_R
Lin_R PGA [ADC_A_PDX]
Interface
DAC 16bit
VDDvh VSSvh VDDv VSSv VDDh VSSh VDDsp VSSsp VDDana VSSana VDDio VDDdig VSSdig G_PORT2 G_PORT1 G_PORT0
DAC 16bit
[ADC_D_PDX] MPU MCLK BCLK LRCLK DAC_Din ADC_Dout CS_X SCLK SDin RESET_X TESTin Serial IF /Regster/ I2S IF
[DAC_D_PDX] [DAC_A_PDX]
No.A1619-20/32
LC07424LP
Line input circuits
ALC_LI_L: ACL LIne select Left channel ALC_LI_R: ALC LIne select Right channel
ADRS 02h Bit [4] Name ALC_LI_L INIT 1b Lch Line input selection 1: Selection 0: Non-selection (LIN_L pin enters the OPEN state.) [0] ALC_LI_R 1b Rch Line input selection 1: Selection 0: Non-selection (LIN_R pin enters the OPEN state.) Description
ALC circuit settings
ALC_VAL ALC_FA ALC_FR ALC_ZCD ALC_ZCDTM ALC_FULLEN ALC_ATLIM ALC_RWT ALC_OFF ALC_VMAX ALC_MUTE_L ALC_DVL ALC_MUTE_R ALC_DVR
ADRS 03h Bit [7:5]
: ALC VALue : ALC Factor Attack : ALC Factor Recovery : ALC Zero Cross Detect : ALC Zero Cross Detect TiMe out : ALC FULL scale detect ENable : ALC ATtack LIMit : ALC Recovery Waiting Time : ALC operation OFF : ALC Value MAX : ALC MUTE Left channel : ALC Digital Value Left channel : ALC MUTE Right channel : ALC Digital Value Right channel
Name ALC_VAL[2:0] INIT 001b Description ALC circuit, ALC value (limiter level) setting *1 111:-10dBFS 110: -9dBFS 101: -8dBFS 100: -7dBFS 011: -6dBFS 010: -5dBFS 001: -4dBFS 000: -3dBFS
[4:3]
ALC_FA[1:0]
11b
ALC circuit, Attack factor setting Gain DOWN amount at fs cycle *2 11: (1 / 8)dB 10: (1 / 4)dB 01: (1 / 2)dB 00: (1 / 1)dB
[2:0]
ALC_FR[2:0]
101b
ALC circuitRecovery factor setting Gain UP amount at fs cycle *3 111: (1 / 2^14)dB 110: (1 / 2^13)dB 101: (1 / 2^12)dB 100: (1 / 2^11)dB 011: (1 / 2^10)dB 010: (1 / 2^9)dB 001: (1 / 2^8)dB 000: (1 / 2^7)dB
*1 For example, -10dBFS (dB Full Scale) is on the level 10 dB lower than the Full Scale. *2 For example, [ALC_FA] = 11b causes 1 dB gain DOWN at the eight cycle of fs. *3 For example, [ALC_FR] = 111b causes 1 dB gain UP at the 2^14 (=16384) cycle of fs.
No.A1619-21/32
LC07424LP
ADRS 04h Bit [7] Name ALC_ZCD INIT 1b Description ALC circuit, Gain change in the zero cross timing 1: Gain changed in the zero cross timing 0: Gain changed without waiting for zero cross timing [6:5] ALC_ZCDTM[1:0] 00b ALC circuit, Time setting for timeout at zero cross detection Effective when [ALC_ZCD]=1 11: 8192 (1 / fs) 10: 4096 (1 / fs) 01: 2048 (1 / fs) 00: 1024 (1 / fs) [4] ALC_FULLEN 0b ALC circuit, Full scale detection operation setting Rapid level down at detection of full scale 1: ON 0: OFF [3:2] ALC_ATLIM[1:0] 01b ALC circuit, Limit setting for the attack operation frequency between zero crosses effective when [ALC_ZCD]=1. For the actual reduction for the frequency, See Table 1. 11: 16 10: 8 01: 4 00: 2 [1:0] 05h [7] ALC_RWT[1:0] ALC_OFF 10b 0b ALC circuit, Standby time setting during recovery operation. 11: 2048 (1 / fs) 10: 1024 (1 / fs) 01: 512 (1 / fs) 00: 256 (1 / fs) ALC circuit, Operation stop 1: Operation stop (manual mode) [ALC_DVL] and [ALC_DVR] become effective. 0: Normal operation [6:0] 06h [7] [6:0] 07h [7] [6:0] ALC_VMAX[6:0] ALC_MUTE_L ALC_DVL[6:0] ALC_MUTE_R ALC_DVR[6:0] 1Ch 0b 1Ch 0b 1Ch ALC circuit, PGA maximum gain value setting during ALC operation See Table 8.2. ALC circuit, PGA MUTE setting (Lch) 1: ON 0: OFF ALC circuit, Lch PGA gain value setting in the manual mode See Table 8.2. ALC circuit, PGA MUTE setting (Rch) 1: ON 0: OFF ALC circuit, Rch PGA gain value setting in the manual mode See Table 8.2.
Refer to "Description of ALC operation." Table 8.1. "Reduction value for the set frequency"
[ALC_ATLIM] 11b 10b 01b 00b No, of times 16 8 4 2 [ALC_FA] 11b 2 dB 1 dB 0.5 dB 0.25 dB 10b 4 dB 2 dB 1 dB 0.5 dB 01b 8 dB 4 dB 2 dB 1 dB 00b 16 dB 8 dB 4 dB 2 dB
No.A1619-22/32
LC07424LP
Table 8.2 ALC circuit gain setting table (TYP value) ALC_VMAX[6: 0] / ALC_DVL[6: 0] / ALC_DVL [6: 0]
[6: 0] 7Fh 7Eh 7Dh 7Ch 7Bh 7Ah 79h 78h 77h 76h 75h 74h 73h 72h 71h 70h 6Fh 6Eh 6Dh 6Ch 6Bh 6Ah 69h 68h 67h 66h 65h 64h 63h 62h 61h 60h 34 gain (dB) Set prohibition [6: 0] 5Fh 5Eh 5Dh 5Ch 5Bh 5Ah 59h 58h 57h 56h 55h 54h 53h 52h 51h 50h 4Fh 4Eh 4Dh 4Ch 4Bh 4Ah 49h 48h 47h 46h 45h 44h 43h 42h 41h 40h gain (dB) 33.5 33.0 32.5 32.0 31.5 31.0 30.5 30.0 29.5 29.0 28.5 28.0 27.5 27.0 26.5 26.0 25.5 25.0 24.5 24.0 23.5 23.0 22.5 22.0 21.5 21.0 20.5 20.0 19.5 19.0 18.5 18.0 [6: 0] 3Fh 3Eh 3Dh 3Ch 3Bh 3Ah 39h 38h 37h 36h 35h 34h 33h 32h 31h 30h 2Fh 2Eh 2Dh 2Ch 2Bh 2Ah 29h 28h 27h 26h 25h 24h 23h 22h 21h 20h gain (dB) 17.5 17.0 16.5 16.0 15.5 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 [6: 0] 1Fh 1Eh 1Dh 1Ch 1Bh 1Ah 19h 18h 17h 16h 15h 14h 13h 12h 11h 10h 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 08h 07h 06h 05h 04h 03h 02h 01h 00h gain (dB) 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 -5.5 -6.0 -6.5 -7.0 -7.5 -8.0 -8.5 -9.0 -9.5 -10.0 -10.5 -11.0 -11.5 -12.0 -12.5 -13.0 -13.5 -14.0
No.A1619-23/32
LC07424LP
Audio data format, Other
ADF_BCLK : Audio Data Format BCLK ADF_MODE : Audio Data Format MODE ADF_DAC_INV : Audio Data Format DAC data INVert ADF_ADC_INV : Audio Data Format ADC data INVert DE_EN : De-Emphasis filter ENable ADF_FS : Audio Data Format Frequency Sampling ADF_LB : Audio Data Format Loop Back ADF_MASTER : Audio Data Format MASTER mode
ADRS 09h Bit [4] [1:0] 0Ah [7] [6] [4] Name ADF_BCLK ADF_MODE[1:0] ADF_DAC_INV ADF_DAC_INV DE_EN INIT 0b 00b 0b 0b 0b See Table 8.3. Audio data format setting See Table 8.3. DAC input data inverted setting 1: Inverted 0: Non-inversion ADC output data inverted setting 1: Inverted 0: Non-inversion De-Emphasis Filter setting 1: De-Emphasis Filter Effective 0: De-Emphasis Filter Not effective [3:2] ADF_FS[1:0] 00b Sampling Frequency Setting 11: Set prohibition 10: 44.1kHz 01: 32kHz 00: 48kHz [1] ADF_LB 0b Loop back mode select. See Fig. 8.1. 1: ON (ADC output data becomes the DAC input data.) 0: OFF (Normal operation. DAC_DIN pin input becomes the DAC input data.) [0] ADF_MASTER 0b Master / Slave mode setting (IO control of BCLK and LRCLK pins ) 1: Master mode (BCLK and LRCLK pins for output) 0: Slave mode (BCLK and LRCLK pins for input) Description Bit clock frequency setting of audio data format
"7. Audio data format."
Loop back function
This function connects internally ADC_DOUT and DAC_DIN signals. This will enable the ADC input signal to go through to the DAC output. In this case, the ADC_DOUT pin output signal is effective, but the DAC_DIN pin input becomes ineffective.
[ADF_LB] ADC DAC OFF I2S IF ON ADC_DOUT pin DAC_DIN pin
Table 8.3 ADF setting
[ADF_MODE] 11 10 01 00 10 01 00 [ADF_BCLK] 1 1 1 0 0 0 Set prohibition Backward justification 32fs Forward justification 32fs I2S 32fs Backward justification 64fs Forward justification 64fs I2S 64fs
Fig.8.1. Loop back circuit
Selector, Mixer circuit
SEL_L SEL_R MIX_MONO
ADRS 0Bh Bit [7:6] [5:4] [1:0] SEL_L SEL_R MIX_MONO
: SELctor Lch : SELctor Rch : MIXer MONO
Name Init 10b 10b 11b Selector circuit. Lch signal selection 10: DAC output selection 01: ALC / PGA output selection 11, 00: Set prohibition Selector circuit. Rch signal selection 10: DAC output selection 01: ALC / PGA output selection 11, 00: Set prohibition MIX circuit, Setting 11: Lch+Rch setting 10: Rch setting 01: Lch setting 00: Set prohibition Description
No.A1619-24/32
LC07424LP
Speaker amplifier circuits
SP_GAIN SP_ZCD SP_ZCDTM SP_SOFTSW SP_SSC
ADRS 0Ch 0Eh Bit [5:0] [5]
: SPeaker evr GAIN : SPeaker Zero Cross Detect : SPeaker Zero Cross Detect TiMe out : SPeaker SOFT SWitch : SPeaker Soft Switch time Control
Name SP_GAIN SP_ZCD Init 00b 1b See Table 8.4. Speaker amplifier circuit. Gain change in the zero cross timing. 1: Gain changed in the zero cross timing 0: Gain changed without waiting for the zero cross timing Description Gain setting for the speaker amplifier circuit and EVR circuit
[4:3] [2] [1:0]
SP_ZCDTM SP_SOFTSW SP_SSC
01b 1b 11b
Speaker amplifier circuit. Time setting at zero cross timeout 11:1024 (1 / fs) 10: 512 (1 / fs) 01: 256 (1 / fs) 00: 128 (1 / fs) Speaker amplifier circuit. Soft switch function setting 1:ON 0:OFF Speaker amplifier circuit. Time setting when soft switch operates 11: 200ms 10: 100ms 01: 50ms 00: 10ms
Table 8.4. Speaker EVR circuit gain setting (TYP value)
[SP_GAIN] 3Fh 3Eh 3Dh 3Ch 3Bh 3Ah 39h 38h 37h 36h 35h 34h 33h 32h 31h 30h gain (dB) 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 [SP_GAIN] 2Fh 2Eh 2Dh 2Ch 2Bh 2Ah 29h 28h 27h 26h 25h 24h 23h 22h 21h 20h gain(dB) -2.2 -2.4 -2.6 -2.7 -2.9 -3.3 -3.6 -3.9 -4.1 -4.4 -5.0 -5.4 -6.0 -6.5 -6.9 -7.6 [SP_GAIN] 1Fh 1Eh 1Dh 1Ch 1Bh 1Ah 19h 18h 17h 16h 15h 14h 13h 12h 11h 10h gain (dB) -8.4 -9.2 -10.0 -10.7 -11.5 -12.1 -12.9 -13.8 -14.9 -15.7 -16.8 -17.8 -18.8 -19.7 -21.3 -22.8 [SP_GAIN] 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 08h 07h 06h 05h 04h 03h 02h 01h 00h gain (dB) -24.6 -26.2 -28.0 -30.4 -32.4 -35.0 -37.5 -39.7 -42.6 -45.8 -48.7 -51.8 -54.7 -57.8 -60.8 -65.2
No.A1619-25/32
LC07424LP
Line out circuit
LO_DET_VDD: Line Out DETct VDDh LO_GAIN : Line Out GAIN LO_VREFSW : Line Out Voltage REFerence SWitch LO_MUTE : Line Out MUTE
ADRS 0Fh Bit [3] [2] [1] Name LO_DET_VDD LO_GAIN LO_VREFSW Init 1b 1b 1b 1: ON 0: OFF Description Line output. VDDh power detection function Line output. Amplifier gain setting 1: 6.5dB 0: 0dB Line output. Effective for pin state control and power DOWN ([LO_PDX]=0) 1: LOUT_L and LOUT_R pins become the VREF level output. 0: LOUT_L and LOUT_R pins become Hi-Z. [0] LO_MUTE 1b Line output. MUTE setting 1: ON 0: OFF
VDDh power detection function (operation for setting of [LO_MUTE]=0 and [LO_PDX]=1) When VDDh power supply becomes 4.0V (TYP) or less, the line output is automatically set to the state equivalent to "[LO_MUTE]=1, [LO_PDX]=0." When VDDh power supply returns to 4.3V (TYP) or more, the line output is automatically set to the state equivalent to "[LO_MUTE]=0, [LO_PDX]=1." Refer to "1. Reference power supply, line out start/stop sequence."
Video circuit
VD_Y_GAIN : Video Driver Y GAIN VD_C_GAIN : Video Driver C GAIN VD_SAG_MODE: Video Driver SAG MODE
ADRS 12h 13h 14h Bit [5:0] [5:0] [1] Name VD_Y_GAIN[5:0] VD_C_GAIN[5:0] VD_SAG_MODE INIT 11h 11h 1b See Table 8.5. Video driver. CIN pin input gain setting See Table 8.5. Video driver. VOUT pin output setting 1: Sag compensation type 0: DC direct coupling type Description Video driver. YIN pin input gain setting
Table 8.5. Video driver circuit gain setting (TYP value)
[5: 0] 3Fh 3Eh 3Dh 3Ch 3Bh 3Ah 39h 38h 37h 36h 35h 34h 33h 32h 31h 30h gain (dB) Set prohibition [5: 0] 2Fh 2Eh 2Dh 2Ch 2Bh 2Ah 29h 28h 27h 26h 25h 24h 23h 22h 21h 20h gain (dB)
VD_Y_GAIN [5: 0] / VD_C_GAIN [5: 0]
[5: 0] 1Fh 1Eh 1Dh 1Ch 1Bh 1Ah 19h 18h 17h 16h 15h 14h 13h 8.2 8.1 8.0 12h 11h 10h gain (dB) 7.9 7.8 7.7 7.6 7.5 7.4 7.3 7.2 7.1 7.0 6.9 6.8 6.7 6.6 6.5 6.4 [5: 0] 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 08h 07h 06h 05h 04h 03h 02h 01h 00h gain (dB) 6.3 6.2 6.1 6.0 5.9 5.8 5.7 5.6 5.5 5.4 5.3 5.2 5.1 5.0 4.9 4.8
Set prohibition
No.A1619-26/32
LC07424LP
Sag compensation type ([VD_SAG_MODE]=1b)
Value (TYP) when DAC output is 1Vp-p and gain setting is 6dB
Sync tip level YIN pin VOUT pin VIDEO 0.8V 1.0V (Note 1) (Note 2) 1Vp-p 2Vp-p 1Vp-p Video signal level
(Note 1) Fluctuation in V cycle because of sag compensation (Note 2) Fluctuation according to the video signal waveform
YIN DAC 1F CIN DAC 0.1F Vref_v_C VREF (1.3V) BUF CLAMP
0.5dB1.7dB (0.1dB/step)
PGA
4.8V Video VOUT 75 VIDEO 6.0dB Vsag 100F 1F 75
+
BUF BIAS PGA
LPF
# Total gain 6.5dB1.7dB (0.1dB / step)
DC direct coupling type ( [VD_SAG_MODE]=0b)
Value (TYP) when DAC output is 1Vp-p and gain setting is 6dB (TYP)
Sync tip level YIN pin VOUT pin VIDEO 0.8V 0.2V (Note 3) 0.1V 1Vp-p 2Vp-p 1Vp-p Video signal level
(Note 3) The sink chip level is lower than the sag compensation type so as to minimize the power dissipation.
YIN DAC 1F CIN DAC 0.1F Vref_v_C
0.5dB1.7dB (0.1dB / step) BUF CLAMP PGA
4.8V Video VOUT 75 VIDEO 6.0dB Vsag 75
+
BUF BIAS VREF (1.3V) PGA
LPF
# Total gain 6.5dB1.7dB (0.1dB / step)
No.A1619-27/32
LC07424LP
Control to reduce the POP sound
Note [xxxx] is a register name. The POP sound can be reduced by performing start/stop in the timing shown below.
Reference power supply, line out start / stop sequence
Common reference power supply [VREF_BIAS[1]] [VREF_BIAS[0]] Vref_H_C pin Vref_C pin Line_out circuit Line_out input signal t2 [LO_PDX] t3 [LO_MUTE] (0.5)VDDh t4b t1 t4a t3 t2 (0.5)VDDh (0.5)VDDana
LOUT_L pin LOUT_R pin
Recommendation value t1 300ms (Rapid charge period with the Vref_H_C pin connection capacity of 1F and the Vref_C pin connection capacity of 4.7F) t2 0ms t3 1ms (Waiting time of MUTE ON / OFF) t4a 300ms (Pull down period) t4b 1ms (Pull down period, at already when LOUT_L, LOUT_R pin is GND level.) * It makes it to 0Fh: [LO_VREFSW] = 1, usually. * [LO_VREFSW] function at power down (LO_PDX = 0) [LO_VREFSW] = 1: LOUT_L, LOUT_R pin becomes VREF level output [LO_VREFSW] = 0: LOUT_L, LOUT_R pin becomes Hi-Z
*
Speaker Amplifier Start / Stop Sequence
Speaker amplifier input signal [SP_PDX] [SP_OUTEN] t1 SPP,SPN pin (Speaker output) t2 t2 t3 t2 t2 (0.5)VDDh t4
Recommendation value t1 1ms (Speaker bias start-up time) t2: [SP_SSC] set time (200ms / 100ms / 50ms / 10ms) t3 1ms t4 1ms * [SP_OUT_EN] must be set to 0 when power down ([SP_PDX] = 0) mode.
*
No.A1619-28/32
LC07424LP
Description of ALC operation
Note [xxxx] is a register name.
The ALC (Automatic Level Control) function performs automatic adjustment so that the audio level becomes the set value. The amplifier gain of PGA (Programmable Gain Amplifier) is automatically controlled so that the ADC output audio level becomes equal to the ALC value [ALC_VAL]. The PGA gain variable range is +34dB to -14dB. This range helps setting the maximum value [ALC_VMAX]. = By setting [ALC_VMAX] to the maximum value (+34dB), the ALC function can be used to the maximum limit. = By setting [ALC_VMAX] to the gain zero (+0dB), there is no gain in the "+" direction. Namely, the operation becomes equivalent to the limiter function.
ALC settings
* Power down function When [ALC_PDX]=0, the ALC circuit enters the power DOWN mode. * System operation This is done by digitally processing and feeding back the ADC data. For this purpose, the ADC function becomes necessary. Therefore, to activate the ALC function; [ALC_PDX]=1 (ALC power DOWN mode OFF ) [ALC_OFF]=0 (ALC function ON) [ADC_A_PDX]=1, [ADC_D_PDX]=1 (ADC activated)
Manual mode (ALC Function OFF)
With [ALC_OFF]=1, the manual mode becomes effective. The PGA gain becomes the [ALC_DVL] and [ALC_DVR] values. ALC operating There are "attack" and "recovery" operations. See the operation chart on the next page. (1) Attack operations When the PGA output exceeds the ALC value [ALC_VAL], the PGA gain is lowered in a ratio of the attack factor [ALC_FA]. With zero cross detection [ALC_ZCD]=1, the gain reduction between zero crosses is limited by the limit value [ALC_ATLIM]. (2) Recovery operations When the PGA output is 2dB less than the ALC value [ALC_VAL] and this state continues for the recovery standby period [ALC_RWT], the PGA gain is increased in a ratio of the recovery factor [ALC_FR]. The PGA gain increase continues while the state in which the gain is 2dB less than the ALC value [ALC_VAL]. The PGA gain increment between zero crosses is maximum 1 dB. Functions common to (1) and (2) * Zero cross detection With [ALC_ZCD]=1, PGA gain change occurs only when the PGA output is in the zero cross timing. With [ALC_ZCD]=0, PGA gain change is made regardless of whether or not PGA output is zero cross. * Zero cross timeout If the PGA output does not zero cross, the zero cross signal is generated internally if there is no zero cross signal for the period of zero cross timeout value [ALC_ZCDTM]. * Average output amplitude control In the attack operation by spike noise, etc., the average output amplitude becomes small. To prevent this, the recover speed is raised automatically above the [ALC_FR] set value in the case of excessively large input for a short period (tSN).
No.A1619-29/32
LC07424LP
ALC Wave Forms
[ALC_VAL] Input signal
PGA after signal
[ALC_VAL] -2dB
a
b
c
d
e
tSN : Short period(ex.Spike Noise) [ALC_VAL] Input signal
PGA after signal
[ALC_VAL] -2dB
AB
Range a, A b, B c, C d, ,D e, E Attack Stable Recovery wait time Recovery Recovery Stable Operating
C
D
PGA gain Rapid reduction Constant Constant Slow increase Increase faster than d Constant
E
Related registers [ALC_FA] Attack factor [ALC_VAL] ALC value [ALC_RWT] Recovery standby time [ALC_FR] Recovery factor [ALC_FR] Recovery factor [ALC_VMAX] PGA gain maximum value
Limiter operation (PGA gain maximum value [ALC_VMAX]= 0dB set)
[ALC_VAL] Input signal
PGA after signal
[ALC_VAL] -2dB
a
b
c
d
tS
ab
In the tS range, the "input" is equivalent to "PGA After" in terms of signal level. (signal level through)
No.A1619-30/32
LC07424LP
Checkpoints
!! The user is responsible for ascertaining whether this IC can be adopted for the mass production sets, including the various conditions for mounting in the set.
* Powr pins are 4.8V, 2.8V, and 1.8V systems. 4.8V system: Analog power supplies (VDDh, VDDvh) 2.8V system: Analog power supplies (VDDana, VDDsp, VDDv) 1.8V system: Digital powr supply (VDDdig), digital IO power supply (VDDio) Connect the decoupling capacitor near the power pin. Refer to our reference substrate data. * Power ON Simultaneous rise and fall while maintaining the voltage sequence. Alternatively, raise starting from the higher voltage (4.8 V system) side and fall starting from the low voltage (1.8 V system) side. The voltage sequence is 4.8V system 2.8V system 1.8V system.
Power supply
Register control
* Set data for all registers including those for the test. Refer to our recommended register data file. * Registers designated as "registers for LSI test" are fixed at the initial value (INIT).
Resetting
* When power has been applied, be sure to reset. (A) or (B) is executed as shown in the figure below. (A) is reset at the same time as the power is first applied. (B) is reset immediately after the power is first applied. The circuit state is uncertain if the reset is not made. It is recommended to set "th" as short as possible. The RESET_X pin input circuit is subject to clock synchronizing processing. Accordingly, the MCLK pin clock input is always necessary even during periods (A) and (B).
Normal operation
95% power startup level Power pin
tD RESET_X (A)
0.2VDDio
MCLK
Clock ON
tH RESET_X (B)
tD
0.2VDDio
MCLK
Clock ON
tD 10s (note that the MCLK input clock frequency is 8MHz or more
No.A1619-31/32
LC07424LP
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This catalog provides information as of January, 2010. Specifications and information herein are subject to change without notice.
PS No.A1619-32/32

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